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DG428/429 vishay siliconix document number: 70063 s-52433?rev. j, 06-sep-99 www.vishay.com 1 single 8-ch/differential 4-ch latchable analog multiplexers

low r ds(on) : 55 low charge injection: 1 pc on-board ttl compatible address latches high speed?t trans : 160 ns break-before-make low power consumption: 0.3 mw improved system accuracy microprocessor bus compatible easily interfaced reduced crosstalk high throughput improved reliability data acquisition systems automatic test equipment avionics and military systems communication systems microprocessor-controlled analog systems medical instrumentation

the DG428/dg429 analog multiplexers have on-chip address and control latches to simplify design in microprocessor based applications. break-before-make switching action protects against momentary crosstalk of adjacent input signals. the DG428 selects one of eight single-ended inputs to a common output, while the dg429 selects one of four differential inputs to a common differential output. an on channel conducts current equally well in both directions. in the off state each channel blocks voltages up to the power supply rails. an enable (en) function allows the user to reset the multiplexer/demultiplexer to all switches off for stacking several devices. all control inputs, address (a x ) and enable (en) are ttl compatible over the full specified operating temperature range. the silicon-gate cmos process enables operation over a wide range of supply voltages. the absolute maximum voltage rating is extended to 44 v. additionally, single supply operation is also allowed and an epitaxial layer prevents latchup. on-board ttl-compatible address latches simplify the digital interface design and reduce board space in bus-controlled systems such as data acquisition systems, process controls, avionics, and ate.

DG428 DG428 wr d rs s 8 a 0 a 1 en a 2 v? gnd s 1 v+ s 2 s 5 s 3 s 6 s 4 s 7 dual-in-line decoders/drivers 1 2 3 4 5 6 7 8 18 17 16 15 14 13 12 11 top view 910 latches plcc 14 15 16 17 18 8 7 6 5 4 1 2 319 20 11 10 913 12 top view en a 2 v? gnd s 1 v+ s 2 s 5 s 3 s 6 4 d nc 8 7 a wr nc rs a latches decoders/drivers 0 1 s s s
DG428/429 vishay siliconix www.vishay.com 2 document number: 70063 s-52433 ? rev. j, 06-sep-99

dg429 dg429 wr d a rs d b a 0 a 1 en gnd v ? v+ s 1a s 1b s 2a s 2b s 3a s 3b s 4a s 4b dual-in-line and soic decoders/drivers 1 2 3 4 5 6 7 8 18 17 16 15 14 13 12 11 top view 910 latches en gnd v ? v dd s 1a s 1b s 2a s 2b s 3a s 3b plcc 14 15 16 17 18 8 7 6 5 4 1 2 319 20 11 10 913 12 top view 4a a nc b 4b a wr nc rs a latches decoders/drivers 0 1 s d d s 8-channel single-ended multiplexer a 2 a 1 a 0 en wr rs on switch latching x x x x 1 maintains previous switch condition reset x x x x x 0 none (latches cleared) transparent operation x x x 0 0 1 none 0 0 0 1 0 1 1 0 0 1 1 0 1 2 0 1 0 1 0 1 3 0 1 1 1 0 1 4 1 0 0 1 0 1 5 1 0 1 1 0 1 6 1 1 0 1 0 1 7 1 1 1 1 0 1 8 differential 4-channel multiplexer a 1 a 0 en wr rs on switch latching x x x 1 maintains previous switch condition reset x x x x 0 none (latches cleared) transparent operation x x 0 0 1 none 0 0 1 0 1 1 0 1 1 0 1 2 1 0 1 0 1 3 1 1 1 0 1 4 logic ? 0 ? = v al 0.8 v logic ? 1 ? = v ah 2.4 v x = don ? t care

temp range package part number 18-pin plastic dip DG428dj ? 40 to 85 c 20-pin plcc DG428dn

temp range package part number 18-pin plastic dip dg429dj ? 40 to 85 c 20-pin plcc dg429dn 18-pin widebody soic dg429dw
DG428/429 vishay siliconix document number: 70063 s-52433 ? rev. j, 06-sep-99 www.vishay.com 3

voltage referenced to v ? v+ 44 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd 25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital inputs a , v s , v d (v ? ) ? 2 v to (v+) +2 v or . . . . . . . . . . . . . . . . . . . . . . . . 30 ma, whichever occurs first current (any terminal) 30 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peak current, s or d (pulsed at 1 ms, 10% duty cycle max) 100 ma . . . . . . . . . . . . . . . . . . . . . . . . storage temperature (ak suffix) ? 65 to 150 c . . . . . . . . . . . . . . . . . . (dj, dn suffix) ? 65 to 125 c . . . . . . . . . . . . . . power dissipation (package) b 18-pin plastic dip c 470 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-pin cerdip d 900 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-pin plcc f 800 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-pin widebody soic f 450 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes: a. signals on s x , d x or in x exceeding v+ or v ? will be clamped by internal diodes. limit forward diode current to maximum current ratings. b. all leads soldered or welded to pc board. c. derate 6.3 mw/ c above 75 c. d. derate 12 mw/ c above 75 c. e. derate 10 mw/ c above 75 c. f. derate 6 mw/ c above 75 c.

test conditions unless otherwise specified a suffix ? 55 to 125 c d suffix ? 40 to 85 c parameter symbol v+ = 15 v, v ? = ? 15 v, wr = 0, rs = 2.4 v, v in = 2.4 v, 0.8 v f temp b typ c min d max d min d max d unit analog switch analog signal range e v analog full ? 15 15 ? 15 15 v drain-source on-resistance r ds(on) v d = 10 v, v al = 0.8 v i s = ? 1 ma, v ah = 2.4 v room full 55 100 125 100 125 greatest change in r ds(on) between channels g r ds(on) ? 10 v < v s < 10 v i s = ? 1 ma room 5 % source off leakage current i s(off) v s = 10 v, v d = 10 v v en = 0 v room full 0.03 ? 0.5 ? 50 0.5 50 ? 0.5 ? 50 0.5 50 drain off v d = 10 v DG428 room full 0.07 ? 1 ? 100 1 100 ? 1 ? 100 1 100 drain off leakage current i d(off) v s = 10 v v en = 0 v dg429 room full 0.05 ? 1 ? 50 1 50 ? 1 ? 50 1 50 na drain on v s = v d = 10 v v en = 2.4 v DG428 room full 0.07 ? 1 ? 100 1 100 ? 1 ? 100 1 100 drain on leakage current i d(on) v en = 2.4 v v al = 0.8 v v ah = 2.4 v dg429 room full 0.05 ? 1 ? 50 1 50 ? 1 ? 50 1 50 digital control logic input current v a = 2.4 v full 0.01 1 1 logic input current input voltage high i ah v a = 15 v full 0.01 1 1 ? 0.01 ? 1 ? 1 dynamic characteristics transition time t trans see figure 5 room full 150 250 300 250 300 break-before-make interval t open see figure 4 full 30 10 10 enable and write turn-on time t on(en,wr) see figures 6 and 7 room full 90 150 225 150 225 ns enable and reset turn-off time t off(en,rs) see figures 6 and 8 room full 55 150 300 150 300 charge injection q v gen = 0 v, r gen = 0 c l = 1 nf, see figure 9 room 1 pc off isolation oirr v en = 0 v, r l = 300 c l = 15 pf v s = 7 v rms, f = 100 khz room ? 75 db source off capacitance c s(off) v s = 0 v, v en = 0 v, f = 1 mhz room 11 DG428 room 40 drain off capacitance c d(off) v d = 0 v, v en = 0 v dg429 room 20 pf v d = 0 v, v en = 0 v f = 1 mhz DG428 room 54 drain on capacitance c d(on) dg429 room 34
DG428/429 vishay siliconix www.vishay.com 4 document number: 70063 s-52433 ? rev. j, 06-sep-99

test conditions unless otherwise specified a suffix ? 55 to 125 c d suffix ? 40 to 85 c parameter symbol v+ = 15 v, v ? = ? 15 v, wr = 0, rs = 2.4 v, v in = 2.4 v, 0.8 v f temp b typ c min d max d min d max d unit minimum input timing requirements write pulse width t w full 100 100 a x , en data set up time t s see figure 2 full 100 100 a x , en data hold time t h full 10 10 ns reset pulse width t rs v s = 5 v, see figure 3 full 100 100 power supplies positive supply current i+ room 20 100 100 ? v en = 0 v, v a = 0, rs = 5 v room ? 0.001 ? 5 ? 5 a

test conditions unless otherwise specified a suffix ? 55 to 125 c d suffix ? 40 to 85 c parameter symbol v+ = 12 v, v ? = 0 v, wr = 0 rs = 2.4 v, v in = 2.4 v, 0.8 v f temp b typ c min d max d min d max d unit analog switch analog signal range e v analog full 0 12 0 12 v drain-source on-resistance r ds(on) v d = +10 v, v al = 0.8 v i s = ? 500 a, v ah = 2.4 v room 80 150 150 r ds(on) match g r ds(on) 0 v < v s < 10 v i s = ? 1 ma room 5 % source off leakage current i s(off) v s = 0 v, 10 v, v d = 10 v, 0 v v en = 0 v room full 0.03 ? 0.5 ? 50 0.5 50 ? 0.5 ? 50 0.5 50 drain off v d = 0 v, 10 v DG428 room full 0.07 ? 1 ? 100 1 100 ? 1 ? 100 1 100 drain off leakage current i d(off) v s = 10 v, 0 v v en = 0 v dg429 room full 0.05 ? 1 ? 50 1 50 ? 1 ? 50 1 50 na drain on v s = v d = 0 v, 10 v v en = 2.4 v DG428 room full 0.07 ? 1 ? 100 1 100 ? 1 ? 100 1 100 drain on leakage current i d(on) v en = 2.4 v v al = 0.8 v v ah = 2.4 v dg429 room full 0.05 ? 1 ? 50 1 50 ? 1 ? 50 1 50 digital control logic input current v a = 2.4 v full 1 1 logic input current input voltage high i ah v a = 12 v full 1 1 ? 1 ? 1 dynamic characteristics transition time t trans s 1 = 10 v/2 v, s 8 = 2 v/ 10 v see figure 5 room full 160 280 350 280 350 break-before-make interval t open see figure 4 room full 40 25 10 25 10 enable and write turn-on time t on(en, wr) s 1 =5 v see figures 6 and 7 room full 110 300 400 300 400 ns enable and reset turn-off time t off(en, rs) s 1 =5 v see figures 6 and 8 room full 70 300 400 300 400 charge injection q v gen = 6 v, r gen = 0 c l = 1 nf, see figure 9 room 4 pc off isolation oirr v en = 0 v, r l = 300 c l = 15 pf v s = 7 v rms, f = 100 khz room ? 75 db
DG428/429 vishay siliconix document number: 70063 s-52433 ? rev. j, 06-sep-99 www.vishay.com 5

test conditions unless otherwise specified a suffix ? 55 to 125 c d suffix ? 40 to 85 c parameter symbol v+ = 12 v, v ? = 0 v, wr = 0 rs = 2.4 v, v in = 2.4 v, 0.8 v f temp b typ c min d max d min d max d unit minimum input timing requirements write pulse width t w full 100 100 a x , en data set up time t s see figure 2 full 100 100 a x , en data hold time t h full 10 10 ns reset pulse width t rs v s = 5 v, see figure 3 full 100 100 power supplies positive supply current i+ v en = 0 v, v a = 0, rs = 5 v room 20 100 100 a notes: a. refer to process option flowchart. b. room = 25 c, full = as determined by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data s heet. e. guaranteed by design, not subject to production test. f. v in = input voltage to perform proper function. g. r ds(on) r ds(on) max ? r ds(on) min r ds(on) ave x 100%
DG428/429 vishay siliconix www.vishay.com 6 document number: 70063 s-52433 ? rev. j, 06-sep-99

0 20 40 60 80 100 120 140 ? 20 ? 16 ? 12 ? 8 ? 4 0 4 8 12 16 20 v d ? drain voltage (v) r ds(on) vs. v d and supply voltage 5 v 8 v 20 v 15 v 12 v 10 v ? 15 ? 10 ? 50 51015 0 10 20 30 40 50 60 70 80 90 100 r ds(on) ? drain-source on-resistance ( 125 c 85 c 25 c ? 40 c ? 55 c v+ = 15 v v ? = ? 15 v r ds vs. v d and temperature r ds(on) ? drain-source on-resistance ( v d ? drain voltage (v) 0 4 8 12 16 20 0 40 80 120 160 200 v d ? drain voltage (v) v ? = 0 v v+ = 7.5 v 10 v 12 v 15 v 20 v r ds(on) ? drain-source on-resistance ( single supply r ds(on) vs. v d and supply ? 15 ? 10 ? 5051015 ? 30 ? 20 ? 10 0 10 20 30 40 i s(off) v+ = 15 v v ? = ? 15 v v s = ? v d for i d(off) v d = v s for i d(on) i d, i s leakage currents vs. analog voltage v s, v d ? source, drain voltage (v) i d(on), i d(off) ? current (pa) i , i sd ? 55 5 25 45 65 85 105 125 1 pa 10 pa 100 pa 1 na 10 na i s (off) i d(on), i d(off) v+ = 15 v v ? = ? 15 v v s, v d = 14 v i d, i s leakages vs. temperature temperature (c ) ? leakage current i , i sd 0 50 100 150 200 250 ? 5 ? 10 ? 15 ? 20 t trans t on(en) t off(en) supply voltage (v) time (ns) switching times vs. power supply voltage ? 35 ? 15 ) ) )
DG428/429 vishay siliconix document number: 70063 s-52433 ? rev. j, 06-sep-99 www.vishay.com 7

0 50 100 150 200 250 300 350 5 10 15 20 t trans v ? = 0 v switching times vs. single supply time (ms) t on t off ? 15 ? 10 ? 50 51015 ? 60 ? 40 ? 20 0 20 40 60 charge injection vs. analog voltage v s ? source voltage (v) q ? charge (pc) v+ = 12 v v ? = 0 v 1 k 10 k 100 k 1 m 10 m ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 off-isolation vs. frequency oirr (db) 1 k 10 k 100 k 1 m 10 m ? 8 ? 6 ? 4 ? 2 0 2 4 6 8 i ? i+ i gnd e n = 5 v a x = 0 or 5 v supply current vs. switching frequency supply current (ma) f ? frequency (hz) f ? frequency (hz) 0 50 100 150 200 ? 55 ? 35 45 85 125 0 0.5 1 1.5 2 2.5 3 0 5 10 15 20 t trans v+ = 15 v v ? = ? 15 v switching times vs. temperature temperature (c ) time (ns) input switching threshold vs. positivesupply voltage v v+ positive ? supply voltage (v) t off t on ? 15 5 65 105 25 v+ = 15 v v ? = ? 15 v th v+ ? positive supply (v) (v)
DG428/429 vishay siliconix www.vishay.com 8 document number: 70063 s-52433 ? rev. j, 06-sep-99

figure 1. s 1 en d v+ s n v ? decode/ drive level shift v+ latches v ref v+ v ? d o d n clk reset q o q n a x wr rs gnd v ?

figure 2. figure 3. 3 v 0 v 3 v 0 v 50% 20% 80% en 3 v 0 v 0 v 50% t w t h wr rs a 0 , a 1 , (a 2 ) v o switch output t rs t off(rs ) t s 80%

figure 4. break-before-make DG428 dg429 en v+ gnd v ? +5 v 35 pf ? 15 v +15 v +2.4 v rs a 0 , a 1 , (a 2 )d b , d all s and d a wr 300 v o 50 logic input switch output v o v s t open t r <20 ns t f <20 ns 3 v 0 v 50% 80% 0 v
DG428/429 vishay siliconix document number: 70063 s-52433 ? rev. j, 06-sep-99 www.vishay.com 9

DG428 dg429 figure 5. transition time s 1b s 1a ? s 4a , d a s 2b and s 3b d b rs a 0 a 1 50 wr 300 v o 10 v 10 v s 4b en v+ gnd v ? 35 pf ? 15 v +15 v +2.4 v rs s 1 s 2 ? s 7 a 0 a 1 a 2 50 wr 300 v o s 8 10 v 10 v en v+ gnd v ? d 35 pf ? 15 v +15 v +2.4 v 3 v 0 v logic input switch output v s8 v o t trans t r <20 ns t f <20 ns s 8 on s 1 on t trans 0 v v s1 50% 10% 90% figure 6. enable t on /t off time DG428 dg429 rs en +2.4 v s 1 s 2 ? s 8 a 0 a 1 a 2 50 wr 300 v o v+ gnd v ? d ? 5 v 35 pf ? 15 v +15 v s 1b s 1a ? s 4a , d a s 2b ? s 4b rs d b a 0 a 1 50 wr 300 v o en +2.4 v v+ gnd v ? ? 5 v 35 pf ? 15 v +15 v logic input switch output v o t r <20 ns t f <20 ns 3 v 0 v 0 v t off(en) t on(en) 50% 90% v o
DG428/429 vishay siliconix www.vishay.com 10 document number: 70063 s-52433 ? rev. j, 06-sep-99

figure 7. write turn-on time t on(wr) 3 v 0 v 0 v 50% DG428 dg429 wr switch output v o 20% t on(wr) a 0 , a 1 , (a 2 ) d b , d en wr 300 remaining switches s 1 or s 1b v o rs v+ gnd v ? +5 v 35 pf ? 15 v +15 v +2.4 v figure 8. reset turn-off time t off(rs) figure 9. charge injection 3 v 0 v 0 v 50% dg42 dg429 rs switch output v o 80% t off(rs) en v o v o v o is the measured voltage error due to charge injection. the charge in coulombs is q = c l x v o off off on rs v o en remaining switches wr s 1 or s 1b d b , d a 0 , a 1 , (a 2 ) 300 v+ gnd v ? +5 v 35 pf ? 15 v +15 v +2.4 v c l 1 nf in d v o 2.4 v rs a 0 , a 1 , (a 2 ) wr v ? v+ s 3 v v g r g ? 15 v gnd +15 v
DG428/429 vishay siliconix document number: 70063 s-52433 ? rev. j, 06-sep-99 www.vishay.com 11

the internal structure of the DG428/dg429 includes a 5-v logic interface with input protection circuitry followed by a latch, level shifter, decoder and finally the switch constructed with parallel n- and p-channel mosfets (see figure 1). the input protection on the logic lines a 0 , a 1 , a 2 , en and control lines wr , rs shown in figure 1 minimizes susceptibility to esd that may be encountered during handling and operational transients. the logic interface is a cmos logic input with its supply voltage from an internal +5 v reference voltage. the output of the input inverter feeds the data input of a d type latch. the level sensitive d latch continuously places the d x input signal on the q x output when the wr input is low, resulting in transparent latch operation. as soon as wr returns high the latch holds the data last present on the d n input, subject to the ? minimum input timing requirements ? table. following the latches the q n signals are level shifted and decoded to provide proper drive levels for the cmos switches. this level shifting ensures full on/off switch operation for any analog signal level between the v+ and v ? supply rails. the en pin is used to enable the address latches during the wr pulse. it can be hard wired to the logic supply or to v+ if one of the channels will always be used (except during a reset) or it can be tied to address decoding circuitry for memory mapped operation. the rs pin is used as a master reset. all latches are cleared regardless of the state of any other latch or control line. the wr pin is used to transfer the state of the address control lines to their latches, except during a reset or when en is low (see truth tables).

bus interfacing the DG428/dg429 minimize the amount of interface hardware between a microprocessor system bus and the analog system being controlled or measured. the internal ttl compatible latches give these multiplexers write-only memory, that is, they can be programmed to stay in a particular switch state (e.g., switch 1 on) until the microprocessor determines it is necessary to turn different switches on or turn all switches off (see figure 10). the input latches become transparent when wr is held low; therefore, these multiplexers operate by direct command of the coded switch state on a 2 , a 1 , a 0 . in this mode the DG428 is identical to the popular dg408. the same is true of the dg429 versus the popular dg409. during system power-up, rs would be low, maintaining all eight switches in the off state. after rs returned high the DG428 maintains all switches in the off state. when the system program performs a write operation to the address assigned to the DG428, the address decoder provides a cs active low signal which is gated with the write (wr ) control signal. at this time the data on the data bus (that will determine which switch to close) is stabilizing. when the wr signal returns to the high state, (positive edge) the input latches of the DG428 save the data from the data bus. the coded information in the a 0 , a 1 , a 2 and en latches is decoded and the appropriate switch is turned on. the en latch allows all switches to be turned off under program control. this becomes useful when two or more DG428s are cascaded to build 16-line and larger multiplexers. data bus reset address decoder address bus +5 v v+ v ? d +15 v ? 15 v DG428 processor system bus 15 v analog inputs analog output wr rs s 1 s 8 a 0 , a 1 , a 2 , en write figure 10. bus interface

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